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New concept of nm manufacturing process

The manufacturing process of the chip is often expressed by 90nm, 65nm, 40nm, 28nm, 22nm, 14nm. For example, Intel's latest six-generation Core series CPU adopts Intel's own 14nm manufacturing process. The current CPU integrates hundreds of millions of transistors, which consist of a source, a drain, and a gate between them. Current flows from the source to the drain, and the gate controls the current on and off. The role.

The so-called nm actually refers to the width of the gate of the complementary oxide metal-semiconductor field-effect transistor formed on the CPU, which is also called the gate length. The shorter the gate length, the more transistors can be integrated on the same size of silicon - Intel once claimed that reducing the gate length from 130nm to 90nm, the area occupied by the transistor will be reduced by half; In a rare case, using a more advanced manufacturing process, the chip area and power consumption are smaller and the cost is lower.

The gate length can be divided into a photolithography gate length and an actual gate length, and the photolithography gate length is determined by photolithography technology. Due to the diffraction phenomenon of light in lithography and the steps of ion implantation, etching, plasma rinsing, heat treatment, etc. in the manufacture of the chip, the lithography gate length and the actual gate length may be inconsistent. In addition, under the same process technology, the actual gate length will be different. For example, although Samsung also introduced a 14nm process chip, the actual gate length of the chip and the actual gate length of Intel's 14nm process chip still have a certain gap.

 Why is 7nm the physical limit?

Shortening the length of the transistor gate allows the CPU to integrate more transistors or effectively reduce transistor area and power consumption, and reduce CPU silicon cost. For this reason, CPU manufacturers have spared no effort to reduce the transistor gate width to increase the number of transistors integrated per unit area. However, this method also shortens the distance of electron movement, which easily causes the electrons in the transistor to spontaneously flow from the negative electrode to the positive electrode through the silicon substrate of the transistor channel, that is, leakage. Moreover, as the number of transistors in the chip increases, the silicon oxide insulating layer, which is originally only a few atomic layers thick, becomes thinner and leads to leakage of more electrons, and then the leakage current increases the additional power consumption of the chip.

In order to solve the problem of leakage, Intel, IBM and other companies can be said to be eight immortals across the sea. For example, Intel has integrated high dielectric thin films and metal gate integrated circuits to solve the leakage problem in its manufacturing process; IBM developed SOI technology to lay a layer of strong dielectric film on the source and drain to solve the leakage problem; Fin-type field effect transistor technology - by increasing the surface area of the insulating layer to increase the capacitance value, reducing leakage current to prevent the occurrence of electronic transitions...

The above method can effectively solve the leakage problem to a certain extent when the gate length is greater than 7 nm. However, on the basis of the existing chip materials, once the transistor gate length is lower than 7 nm, the electrons in the transistor are likely to have a tunneling effect, which poses a huge challenge for the manufacture of the chip. In response to this problem, finding a new material to replace silicon to make transistors below 7nm is an effective solution.

 The 1nm process transistor is still in the laboratory stage, perhaps close at hand, just a stone's throw away...

Carbon nanotubes are related to the very hot graphene in recent years. Zero-dimensional fullerene, one-dimensional carbon nanotubes and two-dimensional graphene belong to the carbon nanomaterial family, and they can form in form after satisfying certain conditions. Conversion. Carbon nanotubes are a one-dimensional material with a special structure. The radial size can reach the nanometer scale, the axial dimension is micron, and the ends of the tube are generally sealed, so it has great strength and huge The aspect ratio is expected to produce carbon fiber with excellent toughness.

Carbon nanotubes and graphene have similar properties in electrical and mechanical properties, and have good electrical conductivity, mechanical properties and thermal conductivity, which make carbon nanotube composites in supercapacitors, solar cells, displays, bioassays, fuels. Battery and other aspects have a good application prospects. In addition, carbon nanotube composite materials doped with some modifiers have also received extensive attention. For example, a CdTe quantum dot is added to a graphene/carbon nanotube composite electrode to fabricate a photoelectric switch, and a doped metal particle is used to fabricate a field emission device. The foreign media reported that Lawrence Berkeley National Laboratory has reduced the most sophisticated transistor process from 14nm to 1nm, and its transistor is made of carbon nanotube doped molybdenum disulfide. However, this technological achievement is only at the stage of breakthrough in laboratory technology, and there is no commercial mass production capability. Whether the technology will become a mainstream commercial technology in the future remains to be tested.

CPU manufacturing process classification

Manufacturing process


The CPU manufacturing process refers to the process of manufacturing various CPUs, processing various circuits and electronic components, manufacturing wires to connect various components, and the like. The precision of its production is now expressed in nanometers (previously in microns), the higher the precision, the more advanced the production process. More electronic components can be accommodated in the same material, and the finer the connection lines are, which helps to improve the integration of the CPU. The nanometer number of the manufacturing process refers to the distance between the circuit and the circuit within the IC. The trend in manufacturing processes is toward higher density. The higher the density of IC circuit design, the higher the density and more complex circuit design in ICs of the same size. The development and progress of microelectronics technology is mainly due to continuous improvement of process technology. The chip manufacturing process began in 1971 and has experienced 10 micrometers, 6 micrometers, 3 micrometers, 1.5 micrometers, 1 micrometer, 800 nanometers, 600 nanometers, 350 nanometers, 250 nanometers, 180 nanometers, 130 nanometers, 90 nanometers, 65 nanometers, and 45 nanometers. Nano, 32nm, 22nm, has been developed to the current (2015) the latest 14nm, in 2016 Bittin Corporation successfully developed mining chips using the 16nm process. And 10 nanometers will be the development goal of the next generation CPU. On January 13, 2017, Qualcomm officially launched its latest top mobile platform at CES2017, the Qualcomm Snapdragon 835 processor with integrated X16 LTE. The Snapdragon 835 processor is the first mobile platform to be commercially manufactured using a 10 nanometer FinFET process node.

Detailed manufacturing process

Silicon purification


The material for producing chips such as CPU and GPU is semiconductor. The main material at this stage is silicon Si, which is a non-metallic element. From a chemical point of view, it is in the metal element region and non-metal element region of the periodic table. The junction, so the nature of semiconductors, suitable for the manufacture of a variety of tiny transistors, is currently one of the most suitable materials for the manufacture of modern large-scale integrated circuits. In the process of silicon purification, the raw silicon will be melted and placed in a huge quartz furnace. At this time, a seed crystal is placed in the furnace so that the silicon crystal grows around the seed crystal until a nearly perfect single crystal silicon is formed. Previous silicon ingots were mostly 200 mm in diameter, and CPU or GPU manufacturers are increasing the production of 300 mm wafers.

Cutting wafer


The ingot is made and shaped into a perfect cylinder, which is then cut into sheets called wafers. Wafers are really used in the manufacture of CPUs and GPUs. The so-called 'cut wafer' is to use a machine to cut a predetermined silicon wafer from a single crystal silicon rod and divide it into small areas, each of which will become the core of a processor ( Die). In general, the thinner the wafer is cut, the more processor products can be manufactured with the same amount of silicon material.


A photoresist (photoresist) material is applied on the silicon oxide layer obtained by the heat treatment, and the ultraviolet ray is irradiated to the silicon substrate by a template printed with a complicated circuit structure pattern of the processor, and the photoresist is dissolved by the ultraviolet ray. In order to avoid interference with light that is not required to be exposed, a mask must be made to shield these areas. This is a fairly complicated process, and the complexity of each mask is described by 10 GB of data. Etching This is an important operation in the CPU and GPU production process and a major technology in the processor industry. Etching technology pushes the application of light to the limit. The etching uses a very short wavelength of ultraviolet light combined with a large lens. Short-wavelength light will illuminate the photoresist film through the holes of these quartz masks to expose it. Next, the illumination is stopped and the mask is removed, and the exposed photoresist film is washed away with a specific chemical solution, and a layer of silicon adhering to the resist film underneath. The exposed silicon will then be bombarded with atoms, causing the exposed silicon substrate to be partially doped, thereby changing the conductive state of these regions to create a N or P well. In combination with the substrate fabricated above, the gate of the processor is finished.

Repeated stratification


In order to process a new layer of circuit, silicon oxide is grown again, then a layer of polysilicon is deposited, a photoresist is applied, and photolithography and etching processes are repeated to obtain a trench structure containing polysilicon and silicon oxide. Repeat multiple times to form a 3D structure, which is the core of the final CPU and GPU. Metal is used as a conductor in the middle of each layer.


At this time, the CPU or GPU is a piece of wafer, which is not directly usable by the user. It must be enclosed in a ceramic or plastic package so that it can be easily mounted on a circuit board. The package structure is different, but the more advanced the processor package is more complex, the new package can often bring the improvement of the chip's electrical performance and stability, and can indirectly provide a solid and reliable basis for the improvement of the main frequency.

Multiple tests

Testing is an important part of processor manufacturing and a necessary test before a processor leaves the factory. This step will test the electrical performance of the wafer to check for any errors and which steps the errors occurred.

Wafer terminology




Acceptor - An element, such as boron, indium, and gallium used to create a free hole in a semiconductor. The acceptor atoms are required to have one less valence electron than the semiconductor.
受主 - 一种用来在半导体中形成空穴的元素,比如硼、铟和镓。受主原子必须比半导体元素少一价电子
Alignment Precision - Displacement of patterns that occurs during the photolithography process.
套准精度 - 在光刻工艺中转移图形的精度。
Anisotropic - A process of etching that has very little or no undercutting 

 各向异性 - 在蚀刻过程中,只做少量或不做侧向凹刻。
Area Contamination - Any foreign particles or material that are found on the surface of a wafer. This is viewed as discolored or smudged, and it is the result of stains, fingerprints, water spots, etc.
沾污区域 - 任何在晶圆片表面的外来粒子或物质。由沾污、手印和水滴产生的污染。
Azimuth, in Ellipsometry - The angle measured between the plane of incidence and the major axis of the ellipse.
椭圆方位角 - 测量入射面和主晶轴之间的角度。
Backside - The bottom surface of a silicon wafer. (Note: This term is not preferred; instead, use ‘back surface’.)
背面 - 晶圆片的底部表面。(注:不推荐该术语,建议使用“背部表面”)
Base Silicon Layer - The silicon wafer that is located underneath the insulator layer, which supports the silicon film on top of the wafer.
底部硅层 - 在绝缘层下部的晶圆片,是顶部硅层的基础。
Bipolar - Transistors that are able to use both holes and electrons as charge carriers.
双极晶体管 - 能够采用空穴和电子传导电荷的晶体管。
Bonded Wafers - Two silicon wafers that have been bonded together by silicon dioxide, which acts as an insulating layer.
绑定晶圆片 - 两个晶圆片通过二氧化硅层结合到一起,作为绝缘层。
Bonding Interface - The area where the bonding of two wafers occurs.
绑定面 - 两个晶圆片结合的接触区。
Buried Layer - A path of low resistance for a current moving in a device. Many of these dopants are antimony and arsenic.
埋层 - 为了电路电流流动而形成的低电阻路径,搀杂剂是锑和砷。
Buried Oxide Layer (BOX) - The layer that insulates between the two wafers.
氧化埋层(BOX) - 在两个晶圆片间的绝缘层。
Carrier - Valence holes and conduction electrons that are capable of carrying a charge through a solid surface in a silicon wafer.
载流子 - 晶圆片中用来传导电流的空穴或电子。
Chemical-Mechanical Polish (CMP) - A process of flattening and polishing wafers that utilizes both chemical removal and mechanical buffing. It is used during the fabrication process.
化学-机械抛光(CMP) - 平整和抛光晶圆片的工艺,采用化学移除和机械抛光两种方式。此工艺在前道工艺中使用。
Chuck Mark - A mark found on either surface of a wafer, caused by either a robotic end effector, a chuck, or a wand.
卡盘痕迹 - 在晶圆片任意表面发现的由机械手、卡盘或托盘造成的痕迹。
Cleavage Plane - A fracture plane that is preferred.
解理面 - 破裂面
Crack - A mark found on a wafer that is greater than 0.25 mm in length.
裂纹 - 长度大于0.25毫米的晶圆片表面微痕。
Crater - Visible under diffused illumination, a surface imperfection on a wafer that can be distinguished individually.
微坑 - 在扩散照明下可见的,晶圆片表面可区分的缺陷。
Conductivity (electrical) - A measurement of how easily charge carriers can flow throughout a material.
传导性(电学方面) - 一种关于载流子通过物质难易度的测量指标 。
Conductivity Type - The type of charge carriers in a wafer, such as “N-type” and “P-type”.
导电类型 - 晶圆片中载流子的类型,N型和P型。
Contaminant, Particulate (see light point defect)
污染微粒 (参见光点缺陷)
Contamination Area - An area that contains particles that can negatively affect the characteristics of a silicon wafer.
沾污区域 - 部分晶圆片区域被颗粒沾污,造成不利特性影响。
Contamination Particulate - Particles found on the surface of a silicon wafer.
沾污颗粒 - 晶圆片表面上的颗粒。
Crystal Defect - Parts of the crystal that contain vacancies and dislocations that can have an impact on a circuit’s electrical performance.
晶体缺陷 - 部分晶体包含的、会影响电路性能的空隙和层错。
Crystal Indices (see Miller indices)
晶体指数 (参见米勒指数)
Depletion Layer - A region on a wafer that contains an electrical field that sweeps out charge carriers.
耗尽层 - 晶圆片上的电场区域,此区域排除载流子。
Dimple - A concave depression found on the surface of a wafer that is visible to the eye under the correct lighting conditions.
表面起伏 - 在合适的光线下通过肉眼可以发现的晶圆片表面凹陷。
Donor - A contaminate that has donated extra “free” electrons, thus making a wafer “N-Type”.
施主 - 可提供“自由”电子的搀杂物,使晶圆片呈现为N型。
Dopant - An element that contributes an electron or a hole to the conduction process, thus altering the conductivity. Dopants for silicon wafers are found in Groups III and V of the Periodic Table of the Elements.
搀杂剂 - 可以为传导过程提供电子或空穴的元素,此元素可以改变传导特性。晶圆片搀杂 剂可以在元素周期表的III 和 V族元素中发现。
Doping - The process of the donation of an electron or hole to the conduction process by a dopant.
掺杂 - 把搀杂剂掺入半导体,通常通过扩散或离子注入工艺实现。
Edge Chip and Indent - An edge imperfection that is greater than 0.25 mm.
芯片边缘和缩进 - 晶片中不完整的边缘部分超过0.25毫米。
Edge Exclusion Area - The area located between the fixed quality area and the periphery of a wafer. (This varies according to the dimensions of the wafer.)
边缘排除区域 - 位于质量保证区和晶圆片外围之间的区域。(根据晶圆片的尺寸不同而有所不同。)
Edge Exclusion, Nominal (EE) - The distance between the fixed quality area and the periphery of a wafer.
名义上边缘排除(EE) - 质量保证区和晶圆片外围之间的距离。
Edge Profile - The edges of two bonded wafers that have been shaped either chemically or mechanically.
边缘轮廓 - 通过化学或机械方法连接起来的两个晶圆片边缘。
Etch - A process of chemical reactions or physical removal to rid the wafer of excess materials.
蚀刻 - 通过化学反应或物理方法去除晶圆片的多余物质。
Fixed Quality Area (FQA) - The area that is most central on a wafer surface.
质量保证区(FQA) - 晶圆片表面中央的大部分。
Flat - A section of the perimeter of a wafer that has been removed for wafer orientation purposes.
平边 - 晶圆片圆周上的一个小平面,作为晶向定位的依据。
Flat Diameter - The measurement from the center of the flat through the center of the wafer to the opposite edge of the wafer. (Perpendicular to the flat)
平口直径 - 由小平面的中心通过晶圆片中心到对面边缘的直线距离。
Four-Point Probe - Test equipment used to test resistivity of wafers.
四探针 - 测量半导体晶片表面电阻的设备。
Furnace and Thermal Processes - Equipment with a temperature gauge used for processing wafers. A constant temperature is required for the process.
炉管和热处理 - 温度测量的工艺设备,具有恒定的处理温度。
Front Side - The top side of a silicon wafer. (This term is not preferred; use front surface instead.)
正面 - 晶圆片的顶部表面(此术语不推荐,建议使用“前部表面”)。
Goniometer - An instrument used in measuring angles.
角度计 - 用来测量角度的设备。
Gradient, Resistivity (not preferred; see resistivity variation)
电阻梯度 (不推荐使用,参见“电阻变化”)
Groove - A scratch that was not completely polished out.
凹槽 - 没有被完全清除的擦伤。
Hand Scribe Mark - A marking that is hand scratched onto the back surface of a wafer for identification purposes.
手工印记 - 为区分不同的晶圆片而手工在背面做出的标记。
Haze - A mass concentration of surface imperfections, often giving a hazy appearance to the wafer.
雾度 - 晶圆片表面大量的缺陷,常常表现为晶圆片表面呈雾状。
Hole - Similar to a positive charge, this is caused by the absence of a valence electron.
空穴 - 和正电荷类似,是由缺少价电子引起的。
Ingot - A cylindrical solid made of polycrystalline or single crystal silicon from which wafers are cut.
晶锭 - 由多晶或单晶形成的圆柱体,晶圆片由此切割而成。
Laser Light-Scattering Event - A signal pulse that locates surface imperfections on a wafer.
激光散射 - 由晶圆片表面缺陷引起的脉冲信号。
Lay - The main direction of surface texture on a wafer.
层 - 晶圆片表面结构的主要方向。
Light Point Defect (LPD) (Not preferred; see localized light-scatterer)
光点缺陷(LPD) (不推荐使用,参见“局部光散射”)
Lithography - The process used to transfer patterns onto wafers.
光刻 - 从掩膜到圆片转移的过程。
Localized Light-Scatterer - One feature on the surface of a wafer, such as a pit or a scratch that scatters light. It is also called a light point defect.
局部光散射 - 晶圆片表面特征,例如小坑或擦伤导致光线散射,也称为光点缺陷。
Lot - Wafers of similar sizes and characteristics placed together in a shipment.
批次 - 具有相似尺寸和特性的晶圆片一并放置在一个载片器内。
Majority Carrier - A carrier, either a hole or an electron that is dominant in a specific region, such as electrons in an N-Type area.
多数载流子 - 一种载流子,在半导体材料中起支配作用的空穴或电子,例如在N型中是电子。
Mechanical Test Wafer - A silicon wafer used for testing purposes.
机械测试晶圆片 - 用于测试的晶圆片。
Microroughness - Surface roughness with spacing between the impurities with a measurement of less than 100 μm.
微粗糙 - 小于100微米的表面粗糙部分。
Miller Indices, of a Crystallographic Plane - A system that utilizes three numbers to identify plan orientation in a crystal.
 Miller索指数 - 三个整数,用于确定某个并行面。这些整数是来自相同系统的基本向量。
Minimal Conditions or Dimensions - The allowable conditions for determining whether or not a wafer is considered acceptable.
最小条件或方向 - 确定晶圆片是否合格的允许条件。
Minority Carrier - A carrier, either a hole or an electron that is not dominant in a specific region, such as electrons in a P-Type area.
少数载流子 - 在半导体材料中不起支配作用的移动电荷,在P型中是电子,在N型中是空穴。
Mound - A raised defect on the surface of a wafer measuring more than 0.25 mm.
堆垛 - 晶圆片表面超过0.25毫米的缺陷。
Notch - An indent on the edge of a wafer used for orientation purposes.
凹槽 - 晶圆片边缘上用于晶向定位的小凹槽。
Orange Peel - A roughened surface that is visible to the unaided eye.
桔皮 - 可以用肉眼看到的粗糙表面
Orthogonal Misorientation -
直角定向误差 -
Particle - A small piece of material found on a wafer that is not connected with it.
颗粒 - 晶圆片上的细小物质。
Particle Counting - Wafers that are used to test tools for particle contamination.
颗粒计算 - 用来测试晶圆片颗粒污染的测试工具。
Particulate Contamination - Particles found on the surface of a wafer. They appear as bright points when a collineated light is shined on the wafer.
颗粒污染 - 晶圆片表面的颗粒。
Pit - A non-removable imperfection found on the surface of a wafer.
深坑 - 一种晶圆片表面无法消除的缺陷。
Point Defect - A crystal defect that is an impurity, such as a lattice vacancy or an interstitial atom.
点缺陷 - 不纯净的晶缺陷,例如格子空缺或原子空隙。
Preferential Etch -
优先蚀刻 -
Premium Wafer - A wafer that can be used for particle counting, measuring pattern resolution in the photolithography process, and metal contamination monitoring. This wafer has very strict specifications for a specific usage, but looser specifications than the prime wafer.
测试晶圆片 - 影印过程中用于颗粒计算、测量溶解度和检测金属污染的晶圆片。对于具体应用该晶圆片有严格的要求,但是要比主晶圆片要求宽松些。
Primary Orientation Flat - The longest flat found on the wafer.
主定位边 - 晶圆片上最长的定位边。
Process Test Wafer - A wafer that can be used for processes as well as area cleanliness.
加工测试晶圆片 - 用于区域清洁过程中的晶圆片。
Profilometer - A tool that is used for measuring surface topography.
表面形貌剂 - 一种用来测量晶圆片表面形貌的工具。
Resistivity (Electrical) - The amount of difficulty that charged carriers have in moving throughout material.
电阻率(电学方面) - 材料反抗或对抗电荷在其中通过的一种物理特性。
Required - The minimum specifications needed by the customer when ordering wafers.
必需 - 订购晶圆片时客户必须达到的最小规格。
Roughness - The texture found on the surface of the wafer that is spaced very closely together.
粗糙度 - 晶圆片表面间隙很小的纹理。
Saw Marks - Surface irregularities
锯痕 - 表面不规则。
Scan Direction - In the flatness calculation, the direction of the subsites.
扫描方向 - 平整度测量中,局部平面的方向。
Scanner Site Flatness -
局部平整度扫描仪 -
Scratch - A mark that is found on the wafer surface.
擦伤 - 晶圆片表面的痕迹。
Secondary Flat - A flat that is smaller than the primary orientation flat. The position of this flat determines what type the wafer is, and also the orientation of the wafer.
第二定位边 - 比主定位边小的定位边,它的位置决定了晶圆片的类型和晶向。
Shape -
形状 -
Site - An area on the front surface of the wafer that has sides parallel and perpendicular to the primary orientation flat. (This area is rectangular in shape)
局部表面 - 晶圆片前面上平行或垂直于主定位边方向的区域。
Site Array - a neighboring set of sites
局部表面系列 - 一系列的相关局部表面。
Site Flatness -
局部平整 -
Slip - A defect pattern of small ridges found on the surface of the wafer.
划伤 - 晶圆片表面上的小皱造成的缺陷。
Smudge - A defect or contamination found on the wafer caused by fingerprints.
污迹 - 晶圆片上指纹造成的缺陷或污染。
Sori -
Striation - Defects or contaminations found in the shape of a helix.
条痕 - 螺纹上的缺陷或污染。
Subsite, of a Site - An area found within the site, also rectangular. The center of the subsite must be located within the original site.
局部子表面 - 局部表面内的区域,也是矩形的。子站中心必须位于原始站点内部。
Surface Texture - Variations found on the real surface of the wafer that deviate from the reference surface.
表面纹理 - 晶圆片实际面与参考面的差异情况。
Test Wafer - A silicon wafer that is used in manufacturing for monitoring and testing purposes.
测试晶圆片 - 用于生产中监测和测试的晶圆片。
Thickness of Top Silicon Film - The distance found between the face of the top silicon film and the surface of the oxide layer.
顶部硅膜厚度 - 顶部硅层表面和氧化层表面间的距离。
Top Silicon Film - The layer of silicon on which semiconductor devices are placed. This is located on top of the insulating layer.
顶部硅膜 - 生产半导体电路的硅层,位于绝缘层顶部。
Total Indicator Reading (TIR) - The smallest distance between planes on the surface of the wafer.
总计指示剂数(TIR) - 晶圆片表面位面间的最短距离。
Virgin Test Wafer - A wafer that has not been used in manufacturing or other processes.
原始测试晶圆片 - 还没有用于生产或其他流程中的晶圆片。
Void - The lack of any sort of bond (particularly a chemical bond) at the site of bonding.
无效 - 在应该绑定的地方没有绑定(特别是化学绑定)。
Waves - Curves and contours found on the surface of the wafer that can be seen by the naked eye.
波浪 - 晶圆片表面通过肉眼能发现的弯曲和曲线。
Waviness - Widely spaced imperfections on the surface of a wafer.
波纹 - 晶圆片表面经常出现的缺陷。